1. Field of Invention
The present invention relates to a configuration of SIP (System In Package), more particularly to a test configuration of the SIP for enhancing integration or interconnection scan test of memory modules in the SIP.
2. Description of Related Art
Nowadays electronic devices, such as: mobile phones, PDAs (personal digital assistants) and on the likes are required to be compact and weight-light; therefore, a SIP (System In Package) technique is developed. In SIP, several chips or ICs or memory modules are integrated into one package, such as: ASIC (Application Specific Integrated Circuit) and a flash memory (memory module) packaged together to reduce the size as whole. Before being packaged, the ASIC and the flash memory are tested respectively and integrated together when they pass the test. Though the ASIC and the flash memory are good dies before being packaged, they have to be tested again after being packaged. But it is difficult to automatically generate suitable test patterns for the SIP integrating the ASIC and the flash memory.
In prior art, a boundary scan test method is used for interconnection (integration) testing between ASIC and the flash memory in the SIP. To support boundary scan, the ICs must contain scan chain. However, the boundary scan test is not applicable to the flash memory, which does not have the corresponding scan chain circuit. Additionally, it is difficult to automatically create functional patterns for the interconnection test because each creation of pattern is case-specific.
Therefore, a built-in self test (BIST) circuit in the ASIC for automatically generating suitable read/write test patterns based on memory type is required. The testability for the integration of the ASIC and the memory device in SIP is enhanced by this BIST circuit.